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DATE
2009
IEEE
115views Hardware» more  DATE 2009»
14 years 4 months ago
Automated data analysis solutions to silicon debug
Since pre-silicon functional verification is insufficient to detect all design errors, re-spins are often needed due to malfunctions that escape into the silicon. This paper pre...
Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris
ICECCS
2008
IEEE
203views Hardware» more  ICECCS 2008»
14 years 4 months ago
Using AADL to Model a Protocol Stack
In recent trends, the Architecture Analysis and Design Language (AADL) has received increasing attention from safety-critical software development industries. Specific about the A...
Didier Delanote, Stefan Van Baelen, Wouter Joosen,...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 2 months ago
Verifying UML/OCL models using Boolean satisfiability
Abstract--Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesig...
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Mart...
CODES
2007
IEEE
14 years 4 months ago
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology ...
Mark Thompson, Hristo Nikolov, Todor Stefanov, And...
VTS
1999
IEEE
66views Hardware» more  VTS 1999»
14 years 2 months ago
A New Bare Die Test Methodology
1 While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that...
Zao Yang, K.-T. Cheng, K. L. Tai