355 search results - page 17 / 71 » Hardware implementation of a novel genetic algorithm |
AHS
2007
IEEE
13 years 7 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modula...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
—In this paper a new ADC architecture of flash type is proposed. This proposed N-bit flash ADC replaces the (2N -1)-toN encoder with two (2N/2 -1)-to-(N/2) encoders to accomplish...
ISCAS
1993
IEEE
13 years 11 months ago
1993
IEEE
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...