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» Hardware implementation of a novel genetic algorithm
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ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
15 years 7 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar
ASAP
2005
IEEE
93views Hardware» more  ASAP 2005»
15 years 5 months ago
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Sol...
Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael ...
114
Voted
UIST
2009
ACM
15 years 9 months ago
Mouse 2.0: multi-touch meets the mouse
In this paper we present novel input devices that combine the standard capabilities of a computer mouse with multitouch sensing. Our goal is to enrich traditional pointerbased des...
Nicolas Villar, Shahram Izadi, Dan Rosenfeld, Hrvo...
ASPLOS
2010
ACM
15 years 10 months ago
Flexible architectural support for fine-grain scheduling
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis
130
Voted
GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
15 years 10 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang