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» Hardware scheduling support in SMP architectures
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DATE
2008
IEEE
158views Hardware» more  DATE 2008»
14 years 1 months ago
Performance Analysis of SoC Architectures Based on Latency-Rate Servers
This paper presents a method for static performance analysis of SoC architectures. The method is based on a network calculus theory known as LR servers. This network calculus is e...
Jelte Peter Vink, Kees van Berkel, Pieter van der ...
DATE
1999
IEEE
115views Hardware» more  DATE 1999»
13 years 11 months ago
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Systems-onChip (SOC) and automatic generation of a retargetable compiler/simulato...
Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh K...
ICCAD
1997
IEEE
94views Hardware» more  ICCAD 1997»
13 years 11 months ago
High-level scheduling model and control synthesis for a broad range of design applications
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
Chih-Tung Chen, Kayhan Küçük&cced...
ASAP
2004
IEEE
123views Hardware» more  ASAP 2004»
13 years 10 months ago
A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these al...
Fabien Castanier, Alberto Ferrante, Vincenzo Piuri
DAC
2006
ACM
14 years 7 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang