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HIPEAC
2005
Springer
14 years 3 months ago
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations
Detecting and predicting a program’s execution phases are crucial to dynamic optimizations and dynamically adaptable systems. This paper shows that a phase can be associated with...
Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, ...
IPPS
2006
IEEE
14 years 4 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 1 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
SBCCI
2006
ACM
139views VLSI» more  SBCCI 2006»
14 years 4 months ago
Infrastructure for dynamic reconfigurable systems: choices and trade-offs
Platform-based design is a method to implement complex SoCs, avoiding chip design from scratch. A promising evolution of platform-based design are MPSoC. Such generic architecture...
Leandro Möller, Rafael Soares, Ewerson Carval...
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
14 years 7 months ago
A high-performance parallel CAVLC encoder on a fine-grained many-core system
—This paper presents a high-performance parallel context-based adaptive length coding (CAVLC) encoder implemented on a fine-grained many-core system. The software encoder is desi...
Zhibin Xiao, Bevan Baas