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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 9 months ago
Rapid Embedded Hardware/Software System Generation
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya,...
DAC
1996
ACM
14 years 28 days ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
DT
2000
64views more  DT 2000»
13 years 8 months ago
Hardware/Software Codesign and Rapid Prototyping of Embedded Systems
Frank Slomka, Matthias Dörfel, Ralf Münz...
FPL
2007
Springer
124views Hardware» more  FPL 2007»
14 years 3 months ago
A Quantitative Prediction Model for Hardware/Software Partitioning
An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spo...
Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Ga...
DATE
2004
IEEE
139views Hardware» more  DATE 2004»
14 years 16 days ago
Flexible Software Protection Using Hardware/Software Codesign Techniques
A strong level of trust in the software running on an embedded processor is a prerequisite for its widespread deployment in any high-risk system. The expanding field of software p...
Joseph Zambreno, Alok N. Choudhary, Rahul Simha, B...