Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
-- In this paper a Rapid Prototyping Framework and next steps towards the support for interactive Architecture Exploration based on the SPEAR processor core (Scalable Processor for...
Martin Jankela, Wolfgang Puffitsch, Wolfgang Huber
Most present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. In addition, they generally aim to be implemented effici...
Many embedded applications exist where decisions are made using sensitive information. A critical issue in such applications is to ensure that data is accessed only by authorized ...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ri...
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...