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» Hardware support for code integrity in embedded processors
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CODES
2005
IEEE
14 years 1 months ago
Satisfying real-time constraints with custom instructions
Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
Pan Yu, Tulika Mitra
ASPDAC
2009
ACM
110views Hardware» more  ASPDAC 2009»
14 years 2 months ago
A software solution for dynamic stack management on scratch pad memory
Abstract— In an effort to make processors more power efficient scratch pad memory (SPM) have been proposed instead of caches, which can consume majority of processor power. Howe...
Arun Kannan, Aviral Shrivastava, Amit Pabalkar, Jo...
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
14 years 1 months ago
An efficient SNR scalability coding framework hybrid open-close loop FGS coding
Abstract—This paper presents a novel high-efficient hybrid openclose loop based fine granularity scalable (HOCFGS) coding framework supporting different decoding complexity appli...
Xiangyang Ji, Debin Zhao, Wen Gao, Jizheng Xu, Fen...
ASPDAC
2007
ACM
120views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost
The development cost of low-power embedded systems can be significantly reduced by reusing legacy designs and applying proper modifications to meet the new power constraints. The ...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
ETS
2007
IEEE
94views Hardware» more  ETS 2007»
14 years 2 months ago
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...