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» Heterogeneously tagged caches for low-power embedded systems...
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DATE
2004
IEEE
173views Hardware» more  DATE 2004»
13 years 11 months ago
Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
Taeweon Suh, Douglas M. Blough, Hsien-Hsin S. Lee
DAC
2005
ACM
14 years 8 months ago
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs
We propose two novel integration techniques -- bypass and bookkeeping -- in the memory controller to address the cache coherence compatibility issue of a non-shared bus heterogene...
Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 23 days ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
ISCA
2010
IEEE
239views Hardware» more  ISCA 2010»
14 years 13 days ago
Sentry: light-weight auxiliary memory access control
Light-weight, flexible access control, which allows software to regulate reads and writes to any granularity of memory region, can help improve the reliability of today’s multi...
Arrvindh Shriraman, Sandhya Dwarkadas
ICCS
2003
Springer
14 years 17 days ago
Method Call Acceleration in Embedded Java Virtual Machines
Object oriented languages, in particular Java, use a frequent dynamic dispatch mechanism to search for the definition of an invoked method. A method could be defined in more than...
Mourad Debbabi, M. M. Erhioui, Lamia Ketari, Nadia...