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» Hierarchical Interconnect Circuit Models
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VLSID
2002
IEEE
74views VLSI» more  VLSID 2002»
14 years 8 months ago
Interconnect Energy Dissipation in High-Speed ULSI Circuits
- This work presents accurate closed-form expressions for the interconnect energy dissipation in high-speed ULSI circuits. Unlike previous works, the energy is calculated using an ...
Payam Heydari, Massoud Pedram
DATE
2003
IEEE
101views Hardware» more  DATE 2003»
14 years 27 days ago
On Modeling Cross-Talk Faults
Circuit marginality failures in high performance VLSI circuits are projected to increase due to shrinking process geometries and high frequency design techniques. Capacitive cross...
Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, ...
WSC
1997
13 years 9 months ago
A Java Based System for Specifying Hierarchical Control Flow Graph Models
The portion of the Hierarchical Modeling And Simulation System-Java (HiMASS-j) used for specifying Hierarchical Control Flow Graph (HCFG) Models is described. The specification o...
Thorsten Daum, Robert G. Sargent
FCCM
2007
IEEE
137views VLSI» more  FCCM 2007»
14 years 1 months ago
Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array
— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This p...
I. Faik Baskaya, Brian Gestner, Christopher M. Twi...
ISQED
2007
IEEE
106views Hardware» more  ISQED 2007»
14 years 1 months ago
Passive Modeling of Interconnects by Waveform Shaping
In this paper, we propose a new approach to enforcing the passivity of a reduced system of general passive linear time invariant circuits. Instead of making the reduced models pas...
Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGau...