238 search results - page 14 / 48 » Hierarchical Interconnect Circuit Models |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
Abstract— Frequency dependent interconnect analysis is challenging since lumped equivalent circuit models extracted at different frequencies exhibit distinct time and frequency d...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicromete...