238 search results - page 20 / 48 » Hierarchical Interconnect Circuit Models |
IPPS
2002
IEEE
14 years 17 days ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Under modern VLSI technology, process variations greatly affect circuit performance, especially clock skew which is very timing sensitive. Unwanted skew due to process variation f...
TCAD
1998
13 years 7 months ago
1998
— Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
－ We propose a novel oscillation ring (OR) test architecture for testing interconnects in SoC. In addition to stuck-at and open faults, this scheme can detect delay faults and cr...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we propose a generalized block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends structure-preserving model order ...