238 search results - page 32 / 48 » Hierarchical Interconnect Circuit Models |
DELTA
2002
IEEE
14 years 19 days ago
2002
IEEE
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-...
TCAD
2002
13 years 7 months ago
2002
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
A hierarchical scheme with cells and modules is crucial for managing design complexity during a large integrated circuit design. We present a methodology for thermal aware cell-ba...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
DATE
2002
IEEE
14 years 19 days ago
2002
IEEE
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...