238 search results - page 41 / 48 » Hierarchical Interconnect Circuit Models |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract— We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilev...
ANSS
2000
IEEE
14 years 3 days ago
2000
IEEE
Computer simulation of switching power converters is complicated by the discontinuous (switching) nature of the converter waveforms. When switching details of the waveforms are of...