238 search results - page 6 / 48 » Hierarchical Interconnect Circuit Models |
DAC
1998
ACM
14 years 8 months ago
1998
ACM
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
— Designers require variational information for robust designs. Characterization of such information can be costly for the novel nanoparticle interconnect process, which utilize ...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper presents a linear time algorithm to reduce a large RC interconnect network into subnetworks which are approximated with lower order equivalent RC circuits. The number o...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
In this paper, we propose a new wideband model order reduction method for interconnect circuits by using a novel adaptive sampling and error estimation scheme. We try to address t...