251 search results - page 12 / 51 » Hierarchical Modeling and Simulation of Large Analog Circuit... |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
DAC
2003
ACM
14 years 24 days ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
IJCNN
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents a simple continuous analog hardware realization of the Random Neural Network (RNN) model. The proposed circuit uses the general principles resulting from the u...
FMSD
2010
13 years 6 months ago
2010
Abstract Modeling and Simulation Aided Verification of Analog/MixedSignal Circuits S. Little and C. Myers (University of Utah, USA) Monday, July 14, 14:00-17:00 4 14:00-14:40 fSpic...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parame...