319 search results - page 56 / 64 » Hierarchical Simulation of a Multiprocessor Architecture |
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
ICPP
2008
IEEE
14 years 1 months ago
2008
IEEE
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
DATE
2010
IEEE
14 years 18 days ago
2010
IEEE
—Multi-Processor System-on-Chips (MPSoCs) exploit task-level parallelism to achieve high computation throughput, but concurrent memory accesses from multiple PEs may cause memory...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
TROB
2002
13 years 7 months ago
2002
We consider the problem of having a team of Unmanned Aerial Vehicles (UAV) and Unmanned Ground Vehicles (UGV) pursue a second team of evaders while concurrently building a map in a...