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DATE
2005
IEEE
104views Hardware» more  DATE 2005»
14 years 2 months ago
Queue Management in Network Processors
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
Ioannis Papaefstathiou, Theofanis Orphanoudakis, G...
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 9 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
SIGMOD
2010
ACM
259views Database» more  SIGMOD 2010»
14 years 11 days ago
An extensible test framework for the Microsoft StreamInsight query processor
Microsoft StreamInsight (StreamInsight, for brevity) is a platform for developing and deploying streaming applications. StreamInsight adopts a deterministic stream model that leve...
Alex Raizman, Asvin Ananthanarayan, Anton Kirilov,...
LSSC
2005
Springer
14 years 2 months ago
Systolic Architecture for Adaptive Censoring CFAR PI Detector
A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adap...
Ivan Garvanov, Christo A. Kabakchiev, Plamen Daska...
CLUSTER
2006
IEEE
14 years 2 months ago
A Simple Synchronous Distributed-Memory Algorithm for the HPCC RandomAccess Benchmark
The RandomAccess benchmark as defined by the High Performance Computing Challenge (HPCC) tests the speed at which a machine can update the elements of a table spread across globa...
Steven J. Plimpton, Ron Brightwell, Courtenay Vaug...