249 search results - page 30 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
SOSP
1993
ACM
13 years 9 months ago
1993
ACM
Research can rarely be performed on large-scale, distributed systems at the level of thousands of workstations. In this paper, we describe the motivating constraints, design princ...
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design ...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cooling. To address these challenges, thermal analy...