733 search results - page 118 / 147 » High performance in tree-based parallel architectures |
HPCA
2001
IEEE
14 years 9 months ago
2001
IEEE
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
EUMAS
2006
13 years 10 months ago
2006
We present a general Multi-Agent System framework for distributed data mining based on a Peer-toPeer model. The framework adopts message-based asynchronous communication and a dyn...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...