733 search results - page 124 / 147 » High performance in tree-based parallel architectures |
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
HPCA
2007
IEEE
14 years 3 months ago
2007
IEEE
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
ICN
2005
Springer
14 years 2 months ago
2005
Springer
It is shown that the de Bruijn graph (dBG) can be used as an architecture for interconnection networks and a suitable structure for parallel computation. Recent works have classiï¬...
SBACPAD
2008
IEEE
14 years 3 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
IEEECGIV
2005
IEEE
14 years 2 months ago
2005
IEEE
Creating a 3-D game engine is not a trivial task as gamers often demand for high quality output with top notch performance in games. In this paper, we show you how various real-ti...