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ICS
2009
Tsinghua U.
14 years 1 months ago
High-performance CUDA kernel execution on FPGAs
In this work, we propose a new FPGA design flow that combines the CUDA programming model from Nvidia with the state of the art high-level synthesis tool AutoPilot from AutoESL, to...
Alexandros Papakonstantinou, Karthik Gururaj, John...
MICRO
2003
IEEE
116views Hardware» more  MICRO 2003»
13 years 12 months ago
Universal Mechanisms for Data-Parallel Architectures
Data-parallel programs are both growing in importance and increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. This paper ...
Karthikeyan Sankaralingam, Stephen W. Keckler, Wil...
CC
2004
Springer
160views System Software» more  CC 2004»
14 years 3 days ago
Elkhound: A Fast, Practical GLR Parser Generator
The Generalized LR (GLR) parsing algorithm is attractive for use in parsing programming languages because it is asymptotically efficient for typical grammars, and can parse with an...
Scott McPeak, George C. Necula
ISCA
1998
IEEE
124views Hardware» more  ISCA 1998»
13 years 11 months ago
Threaded Multiple Path Execution
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...
Steven Wallace, Brad Calder, Dean M. Tullsen
CASES
2007
ACM
13 years 10 months ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall