Sciweavers

1710 search results - page 115 / 342
» High-Level Programs and Program Conditions
Sort
View
IPPS
2006
IEEE
14 years 2 months ago
An automated development framework for a RISC processor with reconfigurable instruction set extensions
By coupling a reconfigurable hardware to a standard processor, high levels of flexibility and adaptability are achieved. However, this approach requires modifications to the compi...
Nikolaos Vassiliadis, George Theodoridis, Spiridon...
APCSAC
2003
IEEE
14 years 1 months ago
Mapping Applications to a Coarse Grain Reconfigurable System
This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIU...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Mi...
ISLPED
2003
ACM
96views Hardware» more  ISLPED 2003»
14 years 1 months ago
Effective graph theoretic techniques for the generalized low power binding problem
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
Azadeh Davoodi, Ankur Srivastava
CC
2003
Springer
102views System Software» more  CC 2003»
14 years 1 months ago
Precision in Practice: A Type-Preserving Java Compiler
Popular mobile code architectures (Java and .NET) include verifiers to check for memory safety and other security properties. Since their formats are relatively high level, suppor...
Christopher League, Zhong Shao, Valery Trifonov
DELTA
2010
IEEE
14 years 1 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston