Sciweavers

738 search results - page 71 / 148
» High-Performance Extensible Indexing
Sort
View
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
14 years 2 days ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
VISUALIZATION
1994
IEEE
13 years 12 months ago
VolVis: A Diversified Volume Visualization System
VolVis is a diversified, easy to use, extensible, high performance, and portable volume visualization system for scientists and engineers as well as for visualization developers a...
Ricardo S. Avila, Taosong He, Lichan Hong, Arie E....
ASPDAC
2004
ACM
158views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
FCCM
2004
IEEE
133views VLSI» more  FCCM 2004»
13 years 11 months ago
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area,...
Zachary K. Baker, Viktor K. Prasanna
INFOCOM
2000
IEEE
13 years 11 months ago
A Modular Approach to Packet Classification: Algorithms and Results
The ability to classify packets according to pre-defined rules is critical to providing many sophisticated value-added services, such as security, QoS, load balancing, traffic acco...
Thomas Y. C. Woo