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ISCAS
1994
IEEE
66views Hardware» more  ISCAS 1994»
13 years 11 months ago
High Speed FIR-Filter Architectures with Scalable Sample Rates
FIR ( nite impulse response) lters are widely used in digital signal processing. In this paper new architectures for high speed FIR lters with programmable coe cients are presente...
Martin Vaupel, Heinrich Meyr
APCCAS
2006
IEEE
373views Hardware» more  APCCAS 2006»
13 years 11 months ago
A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs
A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair compa...
Vipul Katyal, Randall L. Geiger, Degang Chen
ASYNC
2006
IEEE
92views Hardware» more  ASYNC 2006»
14 years 1 months ago
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines
We propose a low-overhead method for delay fault testing in high-speed asynchronous pipelines. The key features of our work are: (i) testing strategies can be administered using l...
Gennette Gill, Ankur Agiwal, Montek Singh, Feng Sh...
ISCAS
2006
IEEE
113views Hardware» more  ISCAS 2006»
14 years 1 months ago
High speed routing lookup IC design for IPv6
— With the growth of Internet users and services, the IP address has been exhausted. In order to solve this problem, the short term solution was presented, i.e., CIDR (Classless ...
Yuan-Sun Chu, Hui-Kai Su, Po-Feng Lin, Ming-Jen Ch...
TSP
2008
158views more  TSP 2008»
13 years 7 months ago
High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
Chao Cheng, Keshab K. Parhi