290 search results - page 26 / 58 » High-Speed MARS Hardware |
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
ASYNC
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving As...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
– This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TSMC 0.25 µm CMOS process. Experime...
ICWN
2007
13 years 9 months ago
2007
—This work presents an efficient data service scheme for location dependent data/objects in a cellular mobile network. It is developed around the hardware structure of cellular ...