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DATE
2005
IEEE
204views Hardware» more  DATE 2005»
14 years 1 months ago
Evaluation of Error-Resilience for Reliable Compression of Test Data
This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an Automatic Test Equipment (ATE) to the...
Hamidreza Hashempour, Luca Schiano, Fabrizio Lomba...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
14 years 25 days ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
ITC
2003
IEEE
158views Hardware» more  ITC 2003»
14 years 24 days ago
Extraction Error Diagnosis and Correction in High-Performance Designs
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikara...
SBACPAD
2003
IEEE
121views Hardware» more  SBACPAD 2003»
14 years 24 days ago
Optimizing Packet Capture on Symmetric Multiprocessing Machines
Traffic monitoring and analysis based on general purpose systems with high speed interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, requires carefully designed software...
Gianluca Varenni, Mario Baldi, Loris Degioanni, Fu...
DATE
2000
IEEE
134views Hardware» more  DATE 2000»
13 years 12 months ago
An on Chip ADC Test Structure
In this paper, a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator ...
Yun-Che Wen, Kuen-Jong Lee