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DATE
2005
IEEE
124views Hardware» more  DATE 2005»
14 years 1 months ago
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
Raoul F. Badaoui, Ranga Vemuri
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 23 days ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
SBACPAD
2003
IEEE
180views Hardware» more  SBACPAD 2003»
14 years 23 days ago
New Parallel Algorithms for Frequent Itemset Mining in Very Large Databases
Frequent itemset mining is a classic problem in data mining. It is a non-supervised process which concerns in finding frequent patterns (or itemsets) hidden in large volumes of d...
Adriano Veloso, Wagner Meira Jr., Srinivasan Parth...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 17 days ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
13 years 12 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...