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ISLPED
1996
ACM
76views Hardware» more  ISLPED 1996»
13 years 11 months ago
Comparison of high speed voltage-scaled conventional and adiabatic circuits
The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energy-recovering logic families. Usin...
David J. Frank
ASPDAC
2007
ACM
82views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation
- In this paper we showed the signal degradation parts in High-speed channel of FB-DiMM system. And we also showed possible countermeasure. For the verification propose and also fo...
Atsushi Hiraishi, Toshio Sugano, Hideki Kusamitsu
IPPS
2000
IEEE
13 years 11 months ago
ATOLL, a New Switched, High Speed Interconnect in Comparison to Myrinet and SCI
Abstract. While standard processors achieve supercomputer performance, a performance gap exists between the interconnect of MPP's and COTS. Standard solutions like Ethernet ca...
Markus Fischer, Ulrich Brüning, Jörg Klu...
ISCAS
2008
IEEE
287views Hardware» more  ISCAS 2008»
14 years 2 months ago
A high speed word level finite field multiplier using reordered normal basis
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad...
DATE
2006
IEEE
85views Hardware» more  DATE 2006»
14 years 1 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner