140 search results - page 8 / 28 » High-level design for asynchronous logic |
ASYNC
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a systematic method for designing of a self-healing asynchronous array in the presence of errors. By adding spare resources in one of three different ways and ...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
A novel method to solve the state encoding problem in Signal Transition Graphs is presented. It is based on the structural theory of Petri nets and can be applied to large specifi...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementati...