Sciweavers

1773 search results - page 29 / 355
» High-level power estimation
Sort
View
ISLPED
1996
ACM
89views Hardware» more  ISLPED 1996»
14 years 2 months ago
A novel methodology for transistor-level power estimation
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, ...
DATE
1999
IEEE
81views Hardware» more  DATE 1999»
14 years 2 months ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
GLOBECOM
2006
IEEE
14 years 4 months ago
An Adaptive-Scaling Tone Reservation Algorithm for PAR Reduction in OFDM Systems
— Existing tone-reservation algorithms (such as the controlled clipper algorithm) for OFDM require a number of iterations to ensure the reduction of Peak-to-Average Power Ratio (...
Luqing Wang, Chintha Tellambura
SBCCI
2005
ACM
122views VLSI» more  SBCCI 2005»
14 years 3 months ago
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Cavigl...
RSP
2000
IEEE
105views Control Systems» more  RSP 2000»
14 years 2 months ago
Processor Models for Retargetable Tools
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...
Rajat Moona