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ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 7 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
VLSID
1999
IEEE
104views VLSI» more  VLSID 1999»
14 years 3 months ago
Interconnect Optimization Strategies for High-Performance VLSI Designs
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
DATE
1998
IEEE
91views Hardware» more  DATE 1998»
14 years 3 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...
ICCD
2008
IEEE
175views Hardware» more  ICCD 2008»
14 years 7 months ago
On-chip high performance signaling using passive compensation
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori ...
ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
14 years 5 months ago
High performance on-chip differential signaling using passive compensation for global communication
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori ...