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» High-precision interconnect analysis
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COMPSAC
2009
IEEE
14 years 2 months ago
Towards Validating Security Protocol Deployment in the Wild
As computing technology becomes increasingly pervasive and interconnected, mobility leads to shorter-lasting relationships between end-points with many different security requirem...
Luca Compagna, Ulrich Flegel, Volkmar Lotz
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
14 years 19 days ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
BMCBI
2006
115views more  BMCBI 2006»
13 years 7 months ago
MitoRes: a resource of nuclear-encoded mitochondrial genes and their products in Metazoa
Background: Mitochondria are sub-cellular organelles that have a central role in energy production and in other metabolic pathways of all eukaryotic respiring cells. In the last f...
Domenico Catalano, Flavio Licciulli, Antonio Turi,...
BMCBI
2007
155views more  BMCBI 2007»
13 years 7 months ago
ProMEX: a mass spectral reference database for proteins and protein phosphorylation sites
Background: In the last decade, techniques were established for the large scale genome-wide analysis of proteins, RNA, and metabolites, and database solutions have been developed ...
Jan Hummel, Michaela Niemann, Stefanie Wienkoop, W...
ISCA
2006
IEEE
130views Hardware» more  ISCA 2006»
13 years 7 months ago
Area-Performance Trade-offs in Tiled Dataflow Architectures
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...