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MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
13 years 11 months ago
Access Region Locality for High-Bandwidth Processor Memory System Design
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
UIST
2010
ACM
13 years 5 months ago
VizWiz: nearly real-time answers to visual questions
Visual information pervades our environment. Vision is used to de cide everything from what we want to eat at a restaurant and which bus route to take to whether our clothes match...
Jeffrey P. Bigham, Chandrika Jayant, Hanjie Ji, Gr...
ISCC
2007
IEEE
136views Communications» more  ISCC 2007»
14 years 1 months ago
Analysis of the IPv4 Address Space Delegation Structure
The Internet has grown tremendously in terms of the number of users who rely on it and the number of organizations that are connected to it. Characterizing how this growth affects...
Anusha Sriraman, Kevin R. B. Butler, Patrick Drew ...
DATE
1998
IEEE
91views Hardware» more  DATE 1998»
13 years 11 months ago
Interconnect Tuning Strategies for High-Performance Ics
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahu...
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
14 years 1 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...