43 search results - page 6 / 9 » Hybrid Cache Architecture for High Speed Packet Processing |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
INFOCOM
2008
IEEE
14 years 1 months ago
2008
IEEE
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
ISCAS
1994
IEEE
13 years 11 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
SAC
2006
ACM
14 years 1 months ago
2006
ACM
The reduction of image reconstruction time is needed to spread the use of PET for research and routine clinical practice. In this purpose, this article presents a hardware/softwar...
INFOCOM
1997
IEEE
13 years 11 months ago
1997
IEEE
A packet scheduler in a quality-of-service QoS network should be sophisticated enough to support stringent QoS constraints at high loads, but it must also have a simple implemen...