121 search results - page 7 / 25 » Hybrid cache architecture with disparate memory technologies |
DATE
2000
IEEE
13 years 11 months ago
2000
IEEE
With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
MICRO
2007
IEEE
14 years 29 days ago
2007
IEEE
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
ASPDAC
2008
ACM
13 years 8 months ago
2008
ACM
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...