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» Impact of Parallel Workloads on NoC Architecture Design
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DATE
2009
IEEE
107views Hardware» more  DATE 2009»
14 years 2 months ago
User-centric design space exploration for heterogeneous Network-on-Chip platforms
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
Chen-Ling Chou, Radu Marculescu
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
14 years 1 months ago
A methodology for mapping multiple use-cases onto networks on chips
A communication-centric design approach, Networks on Chips (NoCs), has emerged as the design paradigm for designing a scalable communication infrastructure for future Systems on C...
Srinivasan Murali, Martijn Coenen, Andrei Radulesc...
TC
2010
13 years 5 months ago
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
—The most pervasive compute operation carried out in almost all bioinformatics applications is pairwise sequence homology detection (or sequence alignment). Due to exponentially ...
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pr...
ICCD
2006
IEEE
94views Hardware» more  ICCD 2006»
14 years 4 months ago
Reliability Support for On-Chip Memories Using Networks-on-Chip
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
Federico Angiolini, David Atienza, Srinivasan Mura...
DAC
2010
ACM
13 years 7 months ago
Virtual channels vs. multiple physical networks: a comparative analysis
Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoi...
Young-Jin Yoon, Nicola Concer, Michele Petracca, L...