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DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DAC
2004
ACM
14 years 9 months ago
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant e
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...
CODES
2006
IEEE
14 years 2 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 3 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
VLSID
2005
IEEE
132views VLSI» more  VLSID 2005»
14 years 9 months ago
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, ...