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» Impact of Technology Scaling in the Clock System Power
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ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 4 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
14 years 5 months ago
A Study on Impact of Leakage Current on Dynamic Power
— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now beco...
Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 5 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
14 years 4 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
FPL
2009
Springer
106views Hardware» more  FPL 2009»
14 years 3 months ago
Low power techniques for Motion Estimation hardware
Motion Estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a nove...
Caglar Kalaycioglu, Onur C. Ulusel, Ilker Hamzaogl...