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DATE
2003
IEEE
131views Hardware» more  DATE 2003»
14 years 3 months ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
14 years 3 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
DATE
2002
IEEE
100views Hardware» more  DATE 2002»
14 years 3 months ago
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors
This paper describes the AccuPower toolset -- a set of simulation tools accurately estimating the power dissipation within a superscalar microprocessor. AccuPower uses a true hard...
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
SRDS
1999
IEEE
14 years 2 months ago
CosNamingFT - A Fault-Tolerant CORBA Naming Service
This paper describes the design and implementation of a fault-tolerant CORBA naming service - CosNamingFT. Every CORBA object is accessed through its Interoperable Object Referenc...
Lau Cheuk Lung, Joni da Silva Fraga, Jean-Marie Fa...
DEXAW
2004
IEEE
170views Database» more  DEXAW 2004»
14 years 1 months ago
On-Line Analytical Processing on Large Databases Managed by Computational Grids
Management of large data repositories integrated into the Grid poses new challenges for Grid research. There already exist several successful Data Grid projects addressing process...
Bernhard Fiser, Umut Onan, Ibrahim Elsayed, Peter ...