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» Implementing LDPC Decoding on Network-on-Chip
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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
14 years 1 months ago
High-throughput decoder for low-density parity-check code
— We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regula...
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Iken...
VTC
2008
IEEE
124views Communications» more  VTC 2008»
14 years 2 months ago
Long Length LDPC Code Construction and the Corresponding Decoder Implementation with Adjustable Parallelism
—In this paper, we propose a class of implementation friendly structured LDPC codes with low error floors. The proposed codes exhibit no apparent error floors as compared with qu...
Chia-Yu Lin, Mong-Kai Ku, Yi-Hsing Chien
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 8 months ago
Implementing LDPC Decoding on Network-on-Chip
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
14 years 2 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 11 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...