49 search results - page 6 / 10 » Implementing LDPC Decoding on Network-on-Chip |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
We propose a new powerful scalable generic parallel and modular architecture well suited to LDPC code decoding. This architecture template has been instantiated in the case of the...
ISMVL
2005
IEEE
14 years 1 months ago
2005
IEEE
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
ICC
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— The design of LDPC decoders with low complexity, high throughput, and good performance is a critical task. A well-known strategy is to design structured codes such as q...
ASAP
2006
IEEE
13 years 9 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...