1688 search results - page 103 / 338 » Implementing Optimizations at Decode Time |
DSD
2005
IEEE
14 years 2 months ago
2005
IEEE
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
IPPS
2002
IEEE
14 years 2 months ago
2002
IEEE
Tiling has long been used to improve cache performance. Recursion has recently been used as a cache-oblivious method of improving cache performance. Both of these techniques are n...
MICRO
1995
IEEE
14 years 25 days ago
1995
IEEE
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
RTAS
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper provides four contributions to the study of optimization techniques for component-based distributed realtime and embedded (DRE) systems. First, we describe key challeng...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...