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» Implementing Optimizations at Decode Time
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DATE
2006
IEEE
85views Hardware» more  DATE 2006»
14 years 3 months ago
Optimizing high speed arithmetic circuits using three-term extraction
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by ext...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
CSB
2004
IEEE
14 years 1 months ago
Space-Conserving Optimal DNA-Protein Alignment
DNA-protein alignment algorithms can be used to discover coding sequences in a genomic sequence, if the corresponding protein derivatives are known. They can also be used to ident...
Pang Ko, Mahesh Narayanan, Anantharaman Kalyanaram...
ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
14 years 26 days ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
CISS
2008
IEEE
14 years 3 months ago
Threshold structure of channel aware distributed scheduling in ad-hoc networks: An optimal stopping view
— As evidenced by measurement data, channel fading and co-channel interference occur on the same time scales, and it is therefore difficult to determine if packet losses are due...
Junshan Zhang
ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
14 years 3 months ago
A novel sequential circuit optimization with clock gating logic
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang