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» Implementing Optimizations at Decode Time
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DAC
2004
ACM
14 years 8 months ago
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. Th...
Kihwan Choi, Ramakrishna Soma, Massoud Pedram
FPL
2006
Springer
103views Hardware» more  FPL 2006»
13 years 11 months ago
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
ASAP
2006
IEEE
108views Hardware» more  ASAP 2006»
13 years 11 months ago
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
Pablo Ituero, Marisa López-Vallejo
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
14 years 4 months ago
Interconnect-centric Array Architectures for Minimum SRAM Access Time
‡ Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are r...
Azeez J. Bhavnagarwala, Stephen V. Kosonocky, Jame...
TIP
1998
125views more  TIP 1998»
13 years 7 months ago
Additive vector decoding of transform coded images
—In a standard transform coding scheme of images or video, the decoder can be implemented by a table-lookup technique without the explicit use of an inverse transformation. In th...
Siu-Wai Wu, Allen Gersho