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» Implementing Optimizations at Decode Time
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ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
15 years 8 months ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell
FSE
2006
Springer
117views Cryptology» more  FSE 2006»
15 years 6 months ago
How Far Can We Go on the x64 Processors?
This paper studies the state-of-the-art software optimization methodology for symmetric cryptographic primitives on the new 64-bit x64 processors, AMD Athlon64 (AMD64) and Intel Pe...
Mitsuru Matsui
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 8 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
IOLTS
2006
IEEE
84views Hardware» more  IOLTS 2006»
15 years 8 months ago
An Improved Technique for Reducing False Alarms Due to Soft Errors
A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every ...
Sandip Kundu, Ilia Polian
94
Voted
NIPS
2003
15 years 3 months ago
An MDP-Based Approach to Online Mechanism Design
Online mechanism design (MD) considers the problem of providing incentives to implement desired system-wide outcomes in systems with self-interested agents that arrive and depart ...
David C. Parkes, Satinder P. Singh