857 search results - page 140 / 172 » Implementing a STARI chip |
MTV
2003
IEEE
14 years 1 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
EH
2002
IEEE
14 years 1 months ago
2002
IEEE
The purpose of this paper is twofold: first, to illustrate a stand-alone board-level evolvable system (SABLES) and its performance, and second to illustrate some problems that occ...