28 search results - page 1 / 6 » Implicates and Reduction Techniques for Temporal Logics |
JELIA
1998
Springer
13 years 11 months ago
1998
Springer
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
DSN
2008
IEEE
13 years 9 months ago
2008
IEEE
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
TACAS
2005
Springer
14 years 29 days ago
2005
Springer
Abstract. Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the proh...