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IPPS
2010
IEEE
13 years 6 months ago
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
Abstract-- Recent studies have shown that cache partitioning is an efficient technique to improve throughput, fairness and Quality of Service (QoS) in CMP processors. The cache par...
Kamil Kedzierski, Miquel Moretó, Francisco ...
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
14 years 3 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
EUROGRAPHICS
2010
Eurographics
14 years 4 months ago
Bidirectional Search for Interactive Motion Synthesis
We present an approach to improve the search efficiency for near-optimal motion synthesis using motion graphs. An optimal or near-optimal path through a motion graph often leads ...
Wan-Yen Lo and Matthias Zwicker
TCAD
1998
114views more  TCAD 1998»
13 years 8 months ago
Behavioral optimization using the manipulation of timing constraints
— We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...
Miodrag Potkonjak, Mani B. Srivastava
IPPS
2008
IEEE
14 years 2 months ago
Low power/area branch prediction using complementary branch predictors
Although high branch prediction accuracy is necessary for high performance, it typically comes at the cost of larger predictor tables and/or more complex prediction algorithms. Un...
Resit Sendag, Joshua J. Yi, Peng-fei Chuang, David...