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DAC
2003
ACM
14 years 26 days ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
DAC
2005
ACM
14 years 8 months ago
Race-condition-aware clock skew scheduling
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
NETGAMES
2003
ACM
14 years 26 days ago
A fair message exchange framework for distributed multi-player games
—This paper presents a framework for message delivery in real-time multi-player distributed interactive games that use the client-server model. Based on this framework, we propos...
Katherine Guo, Sarit Mukherjee, Sampath Rangarajan...
ISPD
2006
ACM
108views Hardware» more  ISPD 2006»
14 years 1 months ago
Statistical clock tree routing for robustness to process variations
Advances in VLSI technology make clock skew more susceptible to process variations. Notwithstanding efficient zero skew routing algorithms, clock skew still limits post-manufactu...
Uday Padmanabhan, Janet Meiling Wang, Jiang Hu
IFIP
1999
Springer
13 years 12 months ago
A Synthesis Algorithm for Modular Design of Pipelined Circuits
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
Maria-Cristina V. Marinescu, Martin C. Rinard